The present specification relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present invention relates to use of silicon containing imaging layers to define gate structures.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to achieving smaller sizes of IC device features is the capability of conventional lithography. Lithography is the process by which a pattern or image is transferred from one medium to another. Conventional IC lithography uses ultra-violet (UV) sensitive photoresist. Ultra-violet light is projected to the photoresist through a reticle or mask to create device patterns on an IC. Conventional IC lithographic processes are limited in their ability to print small features, such as contacts, trenches, polysilicon lines or gate structures.
Generally, conventional lithographic processes (e.g., projection lithography and EUV lithography) do not have sufficient resolution and accuracy to consistently fabricate small features of minimum size. Resolution can be adversely impacted by a number of phenomena including: wavelength of light, diffraction of light, lens aberrations, mechanical stability, contamination, optical properties of resist material, resist contrast, resist swelling, thermal flow of resist, etc. As such, the critical dimensions of contacts, trenches, gates, and, thus, IC devices, are limited in how small they can be.
Another difficulty arising from the continuing small dimensions involved in the creation of gate structures is the tendency in the lithography process to experience resist erosion and pattern collapse during trim etch processes. During trim etch processes, a significant amount of the resist is normally etched away in a vertical direction, resulting in a substantial weakening and thinning of the photoresist. This significant reduction of the vertical dimension or thickness of the photoresist from its untrimmed vertical dimension can promote discontinuity thereof, resulting in the photoresist being incapable of providing effective masking in the fabrication of the gate. The resist thickness erosion occurs during etch processes.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need to prevent resist erosion and pattern collapse during trim etch processes. Yet further, there is a need to use imaging layers to define gate structures having small critical dimensions.
An exemplary embodiment is related to a method of fabricating an integrated circuit (IC). This method can include depositing an inorganic underlayer on top of polysilicon, depositing an imaging layer over the inorganic underlayer, patterning the imaging layer, using the imaging layer as a hard mask to selectively trim etch the inorganic underlayer with an isotropic etch in a controlled manner in a high-density plasma etching system to form a pattern, removing the hard mask imaging layer, and etching the portions of the polysilicon layer using the pattern formed by the inorganic underlayer.
Another exemplary embodiment is related to a method of forming a gate in an integrated circuit. This method can include providing a gate material layer, providing a hard mask layer over the gate material layer, etching the hard mask layer with an undercutting technique, and etching the gate material layer to form gate structures.
Another exemplary embodiment is related to a method of preventing resist erosion and pattern collapse during a trim etch process in the manufacture of a gate structure. This method can include depositing an inorganic hard mask material layer over a polysilicon layer, providing a silicon-containing imaging layer over the inorganic hard mask material layer, patterning the silicon-containing imaging layer according to a pattern of gate structures, removing portions of the inorganic hard mask material layer uncovered by the patterned imaging layer, and removing portions of the polysilicon layer uncovered by the unremoved portions of the inorganic hard mask material layer to form gate structures. The inorganic hard mask material layer has a pattern with widths less than widths of the pattern of the imaging layer.
Other principle features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.